Driving ic and optical print head

ABSTRACT

An optical print head has a light-emitting device  22  having n individual electrodes  28 , p common electrodes  27 , and a plurality of (n×p) light-emitting parts  26  selected by those individual and common electrodes and a driving IC  1  having individual electrodes and m group-selecting terminals CD 1  to CD 40 . A plurality of (q) light-emitting devices  22  are provided for one driving IC  1 , and the number (q) of light-emitting devices  22  is determined by the number (p) of common electrodes  27  provided on each light-emitting device  22  and the number (m) of the group-selecting terminals CD provided on the driving IC  1.

TECHNICAL FIELD

The present invention relates to an optical print head for use as arecording head in a printer or the like. More particularly, the presentinvention relates to a novel driving IC for driving a light-emittingdevice designed to be ready for time-division driving within the device,and to an optical print head employing such a driving IC.

BACKGROUND ART

As is disclosed in Japanese Utility Model Laid-Open No. H6-48887, in aconventional optical print head, a light-emitting device (array) has aplurality of individual electrodes provided on the front surface of thedevice so as to correspond one to one to a plurality of light-emittingparts formed on the device, and has a single electrode provided on theback surface of the device so as to be common to all of thoselight-emitting parts. This makes it impossible to perform time-divisiondriving within a single device. Since it is impossible to performtime-division driving, it is necessary to provide as many individualelectrodes as light-emitting parts. Thus, as the light-emitting partsare formed at higher and higher density, the individual electrodes needto be formed at accordingly high density, making their connection to adriving IC difficult.

To solve this problem, Japanese Patent Application Laid-Open No.H6-163980 proposes a light-emitting device that permits time-divisiondriving within the device. Specifically, a plurality of light-emittingparts arranged on the light-emitting device are divided into p, forexample 2 or 3, groups, a plurality of common electrodes are provided sothat each of them is connected to all the light-emitting parts of one ofthose groups, and n individual electrodes are provided so that each ofthem is connected to p light-emitting parts belonging to differentgroups. Thus, the light-emitting device proposed here is provided withp×n light-emitting parts in total. In this light-emitting device, byselecting one of the p common electrodes on a time-division basis, it ispossible to reduce the number of individual electrodes needed to 1/p thenumber needed conventionally, and thereby make their connection to adriving IC easier.

This light-emitting device can be driven on a time-division basis byusing a driving IC as used conventionally. In this case, however, aseparate driving circuit is additionally necessary to select one of thecommon electrodes on a time-division basis. To avoid this, there hasbeen demand for the development of a versatile driving IC suitable fortime-division driving.

Under these circumstances, the applicant of the present invention onceproposed a driving IC in Japanese Patent Application Laid-Open No.H10-226102, with consideration given to the aforementioned points.However, with the configuration proposed here, it is necessary to changethe order of data input to achieve time-division driving, which involvescomplicated processing of data. Moreover, it is necessary to use as manydriving ICs as light-emitting elements used; that is, it is necessary touse many driving ICs at accordingly high cost. Furthermore, this drivingIC, when applied to light-emitting devices having different resolutions,requires complicated processing of data.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a versatile driving ICsuitable to drive a light-emitting device designed to be ready fortime-division driving. Another object of the present invention is toprovide a driving IC that works with a plurality of types oflight-emitting device having different resolutions. Still another objectof the present invention is to provide a driving IC that permits fastdata input.

To achieve the above objects, according to one aspect of the presentinvention, an optical print head is provided with: a light-emittingdevice comprising n×p light-emitting parts, n first electrodes eachconnected to one terminal of p of the light-emitting parts, and p secondelectrodes each connected to the other terminal of n of thelight-emitting parts, wherein selection among the light-emitting partsis achieved by selecting one among the first electrodes and one amongthe second electrodes; and a driving IC device comprising n first outputterminals connected individually to the first electrodes of thelight-emitting parts and m second output terminals connectedindividually to the second electrodes of the light-emitting parts. Here,in total, q light-emitting devices are provided for one driving ICdevice, and the number q of light-emitting devices is determined by thenumber p of second electrodes provided on each light-emitting device andthe number m of second output terminals provided on each driving ICdevice.

According to another aspect of the present invention, a driving ICdevice for supplying a driving current to a light-emitting device havinga plurality of light-emitting parts arranged in a row is provided with nfirst output terminals each connected to one terminal of mlight-emitting parts and a first drive section connected to the firstoutput terminals. Here, the first drive section is provided with: a datasignal storage circuit for storing at least n×m data signals fed insequentially via r input terminals; a data selecting circuit forselecting and extracting, in groups of n, the data signals stored in thedata signal storage circuit; and a drive circuit for outputting drivesignals individually to the first output terminals on the basis of thedata signals selected by the data selecting circuit.

According to still another aspect of the present invention, an opticalprint head is provided with a light-emitting device having a pluralityof light-emitting parts and a driving IC device for supplying a drivingcurrent to the light-emitting parts of the light-emitting device. Here,the light-emitting device is provided with n first electrodes eachconnected to one terminal of a plurality of light-emitting parts.Moreover, the driving IC device is provided with n first outputterminals connected individually to the first electrodes of thelight-emitting device and a first drive section for outputting thedriving current via the first output terminals. Furthermore, the firstdrive section is provided with a data signal storage circuit for storingat least n×m data signals fed in sequentially via r input terminals, adata selecting circuit for selecting and extracting, in groups of n, thedata signals stored in the data signal storage circuit, and a drivecircuit for outputting drive signals individually to the first outputterminals on the basis of the data signals selected by the dataselecting circuit.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit block diagram of the driving IC of a first and asecond embodiment of the invention.

FIG. 2 is a circuit block diagram of a principal portion of the firstand second embodiments.

FIG. 3 is a timing chart of the first and second embodiments.

FIG. 4 is a plan view of a principal portion of the optical print headof the first embodiment.

FIG. 5 is a plan view of a principal portion of the optical print headof the first embodiment.

FIG. 6 is a plan view of a principal portion of the light-emittingdevice of the first embodiment.

FIG. 7 is a circuit block diagram of the optical print head of the firstand second embodiments.

FIG. 8 is a plan view of a principal portion of the optical print headof the second embodiment.

FIG. 9 is a plan view of a principal portion of the light-emittingdevice of the second embodiment.

FIG. 10 is a circuit block diagram of the driving IC of a thirdembodiment of the invention.

FIG. 11 is a circuit block diagram of a principal portion of the drivingIC of the third embodiment.

FIG. 12 is a circuit diagram of a principal portion (division timingsignal generator circuit) of the third embodiment.

FIG. 13 is a timing chart of the third embodiment.

FIG. 14 is a plan view of a principal portion of the optical print headof the third embodiment.

FIG. 15 is a circuit block diagram of the optical print head of thethird embodiment.

FIG. 16 is a diagram schematically showing the configuration of thecharacteristic portion of the third embodiment.

FIG. 17 is a diagram schematically showing the configuration of thecharacteristic portion when applied to a light-emitting deviceconfigured differently from that of the third embodiment.

FIG. 18 is a diagram schematically showing the configuration of thecharacteristic portion when applied to a light-emitting deviceconfigured differently from that of the third embodiment.

FIG. 19 is a diagram schematically showing the configuration of thecharacteristic portion when applied to a light-emitting deviceconfigured differently from that of the third embodiment.

FIG. 20 is a diagram schematically showing the configuration of thecharacteristic portion when applied to a light-emitting deviceconfigured differently from that of the third embodiment.

FIG. 21 is a diagram schematically showing the configuration of thecharacteristic portion when applied to a light-emitting deviceconfigured differently from that of the third embodiment.

FIG. 22 is a timing chart showing the operation of the optical printhead of FIG. 17.

FIG. 23 is a timing chart showing the operation of the optical printhead of FIG. 19.

FIG. 24 is a timing chart showing the operation of the optical printhead of FIG. 20.

FIG. 25 is a timing chart showing the operation of the optical printhead of FIG. 21.

FIG. 26 is a circuit block diagram of a principal portion of the drivingIC of a fourth embodiment of the invention.

FIG. 27 is a timing chart of the fourth embodiment.

FIG. 28 is a circuit diagram of a principal portion (division timingsignal generator circuit) of the fourth embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to the drawings.

First Embodiment

FIG. 1 is a circuit block diagram showing the basic configuration of thedriving IC of a first and a second embodiment of the invention. FIG. 2is a circuit block diagram of a principal portion of the circuit blockdiagram of FIG. 1, specifically the portion associated with one DO1among a plurality of output terminals DO1 to DO48. First, descriptionswill be given with reference mainly to these figures.

As shown in FIG. 1, the driving IC 1 is provided with an individualterminal section DO consisting of a plurality of (n) output terminalsDO1 to DO48 for driving light-emitting devices (i.e. to be connected tothe individual electrodes 28 described later), a first drive section 2connected to the output terminals DO1 to DO48 to feed predeterminedcurrent outputs as driving signals to them, a common terminal section CDconsisting of a plurality of (m) output terminals CD1 to CD40 forselecting groups (i.e. to be connected to the common electrodes 27described later), and a second drive section 3 connected to the outputterminals CD1 to CD40 to selectively switch them to one of thesupplied-power potentials, for example the ground potential VSS. Thefollowing descriptions deal with a case where n=48 and m=40 as shown inthe figures. However, it is to be understood that the present inventionmay be implemented in any other manner than specifically describedbelow.

The first drive section 2 is provided with a data signal storage circuit4 for temporarily storing serial input data signals that are fed insequentially via a data input terminal SI, a drive circuit 5 foroutputting drive signals individually to the output terminals DO1 toDO48 on the basis of the data signals output from the data signalstorage circuit 4, a current supply circuit 6 for supplying a constantcurrent to the drive circuit 5, and a timing control circuit 7 forfeeding predetermined timing signals to relevant portions of the firstand second drive sections 2 and 3.

The data signal storage circuit 4 is provided with a shift register 8 ofan n×m (1,920) bit type that takes in serially the data signals fed insequentially via the data input terminal SI in synchronism with a clocksignal CLKI and that outputs the data signals serially via a data outputterminal SO, and a latch circuit 9 of an n×m (1,920) bit type that takesin parallel the data signals taken in by the shift register 8 on thebasis of a load signal LOAD 1. The n×m (1,920) data signals outputparallel from the shift register 8 can be fed also to a storage circuit10 without being passed through the latch circuit 9.

In cases where, for example, the data signals are each consisting of aplurality of bits, the shift register 8 and the latch circuit 9 may beconfigured differently to suit the particular cases. For example, theshift register 8 may be configured as a memory of which differentportions are specified by addresses.

The drive circuit 5 is provided with, as its main blocks, a firstselecting circuit 11A that sequentially selects and outputs, in groupsof n, the n×m (1,920) data signals output from the latch circuit 9, anda first drive circuit 12A of an n (48) bit type that outputs apredetermined current via the output terminals DO1 to DO48 on the basisof the output of the first selecting circuit 11A. As required, inaddition to these main blocks, the drive circuit 5 is further providedwith a correction data storage circuit 10 for storing n×m (1,920)correction data signals with which to correct the output current (theamount of light), a second selecting circuit 11B, for correction data,that sequentially selects and outputs, in groups of n, the n×m (1,920)correction data signals output from the correction data storage circuit10, and a second drive circuit 12B, for correction data, that outputs,as driving signals via the output terminals DO1 to DO48, current outputsof which the current is adjusted on the basis of the output from thesecond selecting circuit 11B.

The storage circuit 10 is configured as, for example, a latch circuit ofan S×n×m bit type so that it can store n×m (1,920) correction datasignals each consisting of a plurality of (S) bits (for example, 3bits). The writing of correction data signals to the correction datastorage circuit 10 is achieved on the basis of the signals fed parallel,in groups of n×m, from the shift register 8.

The writing of correction data signals to the correction data storagecircuit 10 can be performed in advance. Specifically, it can beachieved, with the storage circuit 10 alone brought into a write enablestate, by writing one bit of each correction data signal thereto throughthe shift register 8 and repeating this operation S (3) times.

As shown in FIG. 2, the drive circuit 12 is provided with, for eachoutput terminal (for example DO1), a set of a plurality of (in thisexample, four) current amplifiers 12 a to 12 d that output differentcurrent outputs; that is, the drive circuit 12 is provided with as many(in this example, 48) sets of such current amplifiers as the outputterminals arranged in the individual terminal section DO. The fourcurrent amplifiers 12 a to 12 d of each set are fed with a current fromthe current supply circuit 6, and their operation is controlledindividually so that they together yield a total current around 4 mA,variable in the range from 3 to 5 mA.

The selecting circuit 11 is a circuit for selecting and extracting, ingroups of n and thus sequentially at m different times, the n×m datasignals or correction data signals stored in the latch circuit 9 or thecorrection data storage circuit 10 so as to achieve time-divisiondriving. The selecting circuit 11 is composed of a plurality of logicgate circuits. The gates constituting the selecting circuit 11 areopened and closed by a division timing signal generator circuit 14included in the timing control circuit 7.

FIG. 3 shows the waveforms relevant to the division timing signalgenerator circuit 14.

As shown in this figure, the division timing signal generator circuit 14is a circuit for producing m division timing signals DIV1 to DIV40 onthe basis of a control signal DIVSEL that is supplied from outside byway of a small number of (in this example, one) signal lines todetermine the timing of time division. The division timing signalgenerator circuit 14 is composed of, for example, counters. Instead ofcounters, the division timing signal generator circuit 14 may becomposed of decoders or the like that produce m division timing signalsDIV1 to DIV40 on the basis of a control signal DIVSEL that consists of apredetermined number of bits of binary numbers. In this way, thedivision timing signal generator circuit 14 produces m (40) divisiontiming signals (DIV1 to DIV40) on the basis of one control signal DIVSELor a small number of control signals. That is, the control signal DIVSELis fed in by way of a smaller number of signal lines than the number ofdivision timing signals. This makes it possible not only to reduce thenumber of terminals that need to be provided to receive control signalsfrom outside and thereby miniaturize the IC, but also to reduce thenumber of conductors, such as wire-bonded leads, that need to be laid toachieve external connection.

The division timing signal generator circuit 14 can be reset insynchronism with the input of data signals that constitute one line. Thedivision timing signal generator circuit 14 can be reset not only by theuse of a reset signal RESET but also by the use of the load signal LOAD1mentioned earlier.

Next, with reference to FIG. 2, the flow of data will be described withrespect mainly to one output terminal DO1. As the division timingsignals DIV1 to DIV40 are turned to H level one by one, 40 AND gatecircuits provided in the first selecting circuit 11A and connected tothose division timing signals DIV1 to DIV40 and to the latch circuit 9are opened one by one. Thus, the data signals corresponding to the wholeIC that are stored in the latch circuit 9 (1,920 pieces of on/off data)are selectively output through the AND gate circuit that is open at eachmoment. Similarly, as the division timing signals DIV1 to DIV40 areturned to H level one by one, AND gates circuit provided in sets ofthree (in this example, 40 sets in total) in the second selectingcircuit 11B are opened one set after another. Thus, the three-bitcorrection data signals stored in the correction data storage circuit 10are selectively output through the set of AND gate circuits that is openat each moment. The output of the correction data storage circuit 10 isfed to the drive circuit 12 so as to selectively operate, together withthe data signals fed from the latch circuit 9 through the firstselecting circuit 11A, the three current amplifiers 12 b to 12 d.

Next, the second drive section 3 will be described. The second drivesection 3 is a circuit for selectively switching one of the outputterminals CD1 to CD40 to the ground potential VSS. Here, the switchingis achieved on the basis of the division timing signals DIV1 to DIV40.The switching may be achieved by the use of other signals that aresynchronous with the division timing signals DIV1 to DIV40.

As shown in FIG. 5, the driving IC1 has the terminals DO1 to DO48arranged along one side, has the terminals CD1 to CD40 arranged alongtwo opposite sides, with half of them arranged along one side, and hasother terminals for data, clocks, and power supply arranged along theremaining side. That is, the driving IC 1 has terminals having similarfunctions arranged along each side. The terminals DO1 to DO48 arearranged at a density of about 150 DPI (dots per inch). This density isdetermined by the critical density of the fine conductor pattern formedon the substrate 21 described later. Specifically, on the substrate 21,a first and a second conductor pattern 23-1 and 23-2 are laid at adensity of about 150 DPI, and therefore the terminals DOI to DO48 arearranged at a density substantially equal thereto.

FIG. 4 is a plan view schematically showing a principal portion of theoptical print head 20 incorporating the driving IC 1 described above.This optical print head 20 has a plurality of (in this example, L=20)light-emitting devices 22 arranged in a row on an insulating substrate21, and has a smaller number of driving ICs 1 than the light-emittingdevices 22 arranged in a row on one side of the light-emitting devices22. The driving ICs 1 are provided one for every predetermined number qof (in this example, 5) light-emitting devices 22. Thus, one driving IC1 and q light-emitting devices 22 corresponding thereto together formone block (b). A plurality of (in this example, b=4) such blocks arearranged along the longer sides of the substrate 21, and therebyconstitute the optical print head 20.

Between the light-emitting devices 22 and the driving ICs 1 are laidconductors 23 for connecting them together. The conductors 23 includefirst conductors 23-1 for multiplexing that are, at one end, connectedto the output terminals DO1 to DO48 of the driving IC 1 of each blockand that are, at the other end, connected to the individual electrodesof the light-emitting devices 22 within the same block on a commonbasis, and second conductors 23-2 that are, at one end, connected to theoutput terminals CD1 to CD40 for group selection of the driving IC 1 ofeach block and that are, at the other end, connected to the commonelectrodes of the light-emitting elements 22 within the same block on aselective basis. The first conductors 23-1 consist of a conductorpattern for multiplexing that is laid in multiple layers on thesubstrate 21 and wire-bonded leads that connect this pattern to thedriving ICs 1 and to the light-emitting devices 22. Likewise, the secondconductors 23-2 consist of a conductor pattern that is laid in multiplelayers on the substrate 21 and wire-bonded leads that connect thispattern to the driving ICs 1 and to the light-emitting devices 22. Theportions of the conductor patterns constituting the first and secondconductors 23-1 and 23-2 which have substantially the same length as thetotal length along which the light-emitting devices 22 are arranged arearranged separately on both sides of the row of the light-emittingdevices 22. This makes it easier to perform wire-bonding between theconductor patterns and the plurality light-emitting devices 22 as willbe described later.

Of these portions of the patterns of the conductors 23 which arearranged separately on both sides of the row of the light-emittingdevices 22, those belonging to the first conductors 23-2 are smaller innumber than those belonging to the second conductors 23-1, but theformer are larger in both pattern width and interval width than thelatter. Thus, the total width of the portions belonging to the secondconductors 23-2 is larger than that of the portions belonging to thefirst conductors 23-1. The driving ICs 1 and the light-emitting devices22 are connected together in this way, and in addition, of the portionsof the patterns of the conductors 23-1 and 23-2 which are arrangedseparately on both sides of the row of the light-emitting devices 22,those having a larger total width are arranged on one side and thosehaving a smaller total width are, together with the driving ICs 1,arranged on the opposite side. Thus, the light-emitting devices 22 canbe arranged near the center of the substrate 21 in the direction of thewidth thereof. This helps enhance the optical characteristics of theoptical print head as by enhancing the linearity of the arrangement ofthe light-emitting devices 22 (in particular when the substrate 21 ismade of glass epoxy).

The material of the substrate 21 may be, instead of glass epoxy,ceramics or insulating metal. In this example, glass epoxy is usedbecause it makes it easy to lay conductors in multiple layers and toobtain a long substrate, and because it is inexpensive. Irrespective ofwhether the substrate is made of glass epoxy, ceramics, or metal, thecurrent technology permits fine conductors to be laid at a density ofabout 150 DPI at best. The conductors 23 may be realized with, insteadof conductors laid in multiple layers on the substrate 21 andwire-bonded leads of gold or the like, high-density flexible wiresconnected by the use of anisotropic conductive adhesive.

On the substrate 21, separately from the conductors 23, a plurality ofconductor patterns 24 for signal transmission and power supply are laidso as to extend in the direction of arrangement of the light-emittingdevices 22. These conductors include conductors by way of which adjacentdriving ICs 1 are connected together so that they can exchange datasignals and the like. Between the driving ICs 1 and the conductorpatterns 24 are laid wire-bonded leads 25 of gold.

Each light-emitting device 22 has a plurality of (p=n=384)light-emitting parts 26 arranged on the top surface thereof, along thelonger sides thereof and at a density of about 1,200 DPI. Theselight-emitting parts 26 are formed independently of each other so thatthey can be driven on a time-division basis. Specifically, thelight-emitting parts 26 are divided into a plurality of (p) groups sothat they can be driven in groups of n. In this example, thelight-emitting parts 26 are divided into 8 groups on the basis of theremainder that remains when the number representing the order ofarrangement of each light-emitting part 26 is divided by a divisionnumber p (8). Specifically, here, of all the light-emitting parts 26,the first, ninth, seventeenth, . . . belong to a first group, thesecond, tenth, eighteenth, . . . belong to a second group, and so forth.

Moreover, as shown in FIG. 6, on the light-emitting device 22 are laideight common electrodes 27, consisting of a common electrode 27-1 thatis connected to the light-emitting parts 26 belonging to the first groupon a common basis, a common electrode 27-2 that is connected to thelight-emitting parts 26 belonging to the second group on a common basis,. . . , and a common electrode 27-8. Also laid are n (48) individualelectrodes 28 of which each is connected to eight consecutivelight-emitting parts 26. Whereas the common electrodes 27 are arrangedat a density of about 25 DPI, which is lower than the maximum conductordensity (150 DPI) on the substrate 21, the individual electrodes 28 arearranged at a density of about 150 DPI, i.e. at a density substantiallyequal to the maximum conductor density (150 DPI) on the substrate 21. Toreduce the number of conductor layers laid on the surface of thelight-emitting device 22, the common electrodes 27 and the individualelectrodes 28 are arranged on opposite sides of the light-emitting parts26 and along the longer sides of the light-emitting device 22.

This light-emitting device 22 is so configured that the light-emittingparts 26, composed of LEDs, are located at the intersections ofmatrix-like conductors of which some are connected to the p (8) commonelectrodes 27 and the others are connected to n (48) individualelectrodes 28. Thus, by feeding data signals to the n individualelectrodes 28 and selecting one among the common electrodes 27, it ispossible to drive n light-emitting parts 26 simultaneously and, byrepeating this p times, it is possible to drive the whole light-emittingdevice 22.

The individual electrodes 28 are connected individually through thefirst conductors 23-1 to the output terminals DO1 to DO48 of thecorresponding driving IC 1, and the common electrodes 27 are connectedselectively through the second conductors 23-2 to eight among the outputterminals CD1 to CD40 of the same driving IC 1.

As shown in FIG. 7, within a block formed by one driving IC 1 and q (inthis example, light-emitting devices 22 corresponding thereto, theoutput terminals DO1 to DO48 of the driving IC 1 are connected throughthe first conductors 23-1 to the individual electrodes 28 of the qlight-emitting devices 22 on a common basis. The output terminals CD1 toCD40 of the driving IC 1 are connected through the second conductors23-2 to the individual electrodes 27 of the q (5) light-emitting devices22 on an individual basis.

When one among the group-selecting terminals CD1 to CD40 of the drivingIC 1 is selected and predetermined signals are fed to the terminals DO1to DO48, one among the q light-emitting devices 22 is selected, and itslight-emitting parts 26 are lit on a time-division basis, one eighth ofthem at a time. Thus, by repeating this 40 times to select all of thegroup-selecting terminals, it is possible to selectively light all ofthe light-emitting parts 26 within the block.

In this example, q (5) light-emitting devices 22 are provided in oneblock, and there are four such blocks. Thus, in the entire head 20 areprovided b×q×p×n=4×5×8×48 =7,680 light-emitting parts 26 in total.

Next, the operation of the optical print head 20 described above,including the operation of the driving IC 1 of the first embodiment,will be described with reference to, in addition to FIGS. 1 and 2, thetiming chart shown in FIG. 3.

Here, it is assumed that, for the purpose of making the amount of lightemitted by the individual light-emitting parts 26 of the light-emittingdevices 22 even, correction data with which to correct the amount oflight they emit has been determined in advance and already stored in thestorage circuit 10.

First, a reset signal RESET is fed in, which initializes the entireoptical print head. Then, a set signal SET is turned from L level to Hlevel. As a result, the correction data storage circuit 10 is broughtinto a write disable state.

Data signals (7,680 signals) corresponding to one line are sequentiallyfed to the data input terminal SI of the driving IC 1 located at oneend, and are taken in by the shift register 8 of this driving IC 1 insynchronism with the clock signal CLK1. When a predetermined number ofdata signals have been taken in, the data signals are fed through thedata output terminal SO to the shift register 8 of the next IC cascadedto the first IC.

When the data signals corresponding to one line have been taken in andthus data signals are stored in the shift registers 8 of all the drivingICs 1, then the load signal LOAD 1 is held at H level for apredetermined period so that the n×m data signals held in the shiftregister 8 of each driving IC 1 are input. Here, the latch circuit 9selects (latches) data signals on a trailing edge of the load signalLOAD 1, and therefore the n×m data signals taken in by the shiftregister 8 are input to the latch circuit 9 and are stored therein.

Immediately after the load signal LOAD 1 is turned from H level to Llevel, on the basis of a signal DIVSEL supplied from outside as a basefor division timing, the division timing signal generator circuit 14selectively turns the division timing signals DIV1 to DIV40 from L levelto H level. During this timing period, a strobe signal (inverted STB) isturned from H level to L level and is held at L level for apredetermined period.

As the division timing signals DIV1 to DIV40 are switched in this way,the selecting circuit 11 selects and outputs, from one position afteranother, the data signals stored in the latch circuit 9 or thecorrection data storage circuit 10. For example, the division timingsignal DIV1 selects the first, ninth, . . . data signals, and thedivision timing signal DIV2 selects the second, tenth, . . . datasignals.

These data signals (with 3-bit correction data signals added thereto asrequired) are fed to the drive circuit 12. On the basis of the datasignals and the correction data signals added thereto, the drive circuit12 selectively operates the four current amplifiers 12 a to 12 d so thattheir output currents are fed via the output terminals provided in theindividual terminal section DO to the individual electrodes 28 of thelight-emitting devices 22.

In this state, the individual electrodes 28 of all the light-emittingdevices 22 are ready to receive currents corresponding to the datasignals or correction data signals. However, here, only the nlight-emitting parts 26 currently being selected via one of thegroup-selecting terminals are grounded through the common electrodes 27.Thus, in this example, within each block, only one light-emitting device22 is selected, and only every eighth light-emitting part 26 thereof islit selectively.

As described above, by driving a light-emitting device 22 within a blocksequentially at a predetermined number of different times, and repeatingthis a number of times equal to the number of light-emitting devices 22provided in the block, it is possible to achieve time-division driving(p×q=m divisions) so that light is emitted selectively within the block.By performing this in a plurality of blocks simultaneously, it ispossible to emit light that corresponds to one line. By repeating thissequentially, it is possible to achieve the exposure of a whole screenof a electrostatographic printer.

As described above, the driving ICs 1 for driving the light-emittingdevices 22 ready for time-division driving within the devices eachincorporate the second drive section 3 that operates in synchronism withthe timing with which group-by-group driving is performed, and thesedriving ICs 1 drive the corresponding light-emitting devices 22 on atime-division basis. This helps spread the load. Thus, the maximum loadon the second drive section 3 that achieves time-division driving isdetermined by the number of light-emitting parts 26 that belong to onegroup within the corresponding light-emitting devices 22. As a result,as compared with a case where all light-emitting devices are driven on atime-division basis by the use of a dedicated IC for time-divisiondriving (for selection among common electrodes) as in the conventionaldynamic driving method, it is possible to reduce the load on thecircuits that achieve time-division driving.

Moreover, the driving ICs 1 each drive a plurality of light-emittingdevices 22 on a time-division basis. Thus, as compared with a case wherelight-emitting devices 22 and time-division driving ICs are arranged inthe ratio of one to one, it is possible to reduce the number of internalcircuits. In particular with respect to the drive circuits, which occupymore than half of the area of the ICs, whereas it is necessary toprovide q×n drive circuits in a case where light-emitting devices andtime-division driving ICs are arranged in the ratio of one to one, it ispossible to reduce their number to n in the configuration describedabove, achieving a reduction factor of 1/q (=1/5). On the other hand,whereas it is necessary to provide p×q×n drive circuits in a case wherelight-emitting devices and static driving ICs are arranged in the ratioof one to one, it is possible to reduce their number to n in theconfiguration described above, achieving a high reduction factor of1/(p×q) (=1/40). In addition, the driving ICs 1 can be configured tohave the same shape as conventional static ICs, and thus it is possibleto achieve the miniaturization of the overall circuit configuration.

Moreover, despite time-division driving, data can be fed in sequentiallyas in static driving. Thus, there is no need to provide a circuit forrearranging the data as required in conventional time-division driving.Moreover, even when the number of divisions is increased, it is possibleto produce the timing signals DIV1 to DIV40 for time-division driving bythe use of a smaller number of signal lines for control signals than thenumber of division. This makes it possible to reduce the number ofterminals of the IC and the number of assembly steps.

Moreover, the driving ICs 1, despite being ready for time-divisiondriving, can store correction data for all of the light-emitting deviceswithin the same block and selectively output the correction data. Thus,in time-division driving using correction data, it is easy to correctdata signals on the basis of the stored correction data.

This embodiment is suitable for an optical print head in which, asdescribed above, one driving IC and a plurality of light-emittingdevices connected thereto form a block and a plurality of such blocksare arranged in the same direction in which the light-emitting devicesare arranged. However, this embodiment find other application; forexample, it can be applied to an optical print head or other printingdevice that has only one such block as its basic structure.

The configuration of the light-emitting devices connected to the drivingIC described above may be altered according to the specificationsrequired in the optical print head. Specifically, while the number (n)of individual electrodes of each light-emitting device 22 is keptconstant, the number (p) of groups within one light-emitting device 22and the number (q) of light-emitting devices 22 within one block may bechanged as required so that the product of those numbers equals thenumber (m) of group-selecting terminals of the driving IC 1. Forexample, one block may be formed with eight light-emitting devices ofwhich the number (p) of divisions is five. Alternatively, one block maybe formed with ten light-emitting devices of which the number (p) ofdivisions is four. Here, it is possible to select light-emitting deviceshaving light-emitting parts arranged at a different density, and thisenhances the versatility of the driving IC.

In the driving IC described above, the number of time divisions (m) isset at 40. However, by feeding in data in a special manner, it ispossible to change the apparent number of time divisions (the effectivenumber of time divisions) according to the printing speed or the likerequired in the optical print head. For example, in a case wherehigh-speed printing is required and thus the number of time divisionsneed to be changed to a value k that is smaller than m, the dataprocessing circuit that feeds signals to the driving IC 1 is made tooperate in such a way that the effective number of division timingsignals DIV is reduced to k. Specifically, in a case where the divisiontiming signal generator circuit 14 is of an up-counter type, when thenumber of divisions exceeds k, the clock frequency of the control signalDIVSEL is increased so that the remaining timing signals DIVk+1 to DIV40are produced in an extremely short period, and meanwhile the strobesignal (inverted STB) is held at H level so as to inhibit the printingof data in the shortened period. In a case where the division timingsignal generator circuit 14 is of a decoder type, by modifying,according to the desired number k of divisions, the multiple-bit controlsignal DIVSEL that the data processing circuit outputs, it is possibleto selectively produce only the timing signals DIV1 to DIVk. In thisway, by changing the number (m) of divisions of the driving IC 1 so thatthe effective number (k) of divisions is set at, for example, 16,connecting two light-emitting devices 22 as shown in FIG. 6 to thedriving IC 1 to form one block, and arranging ten such blocks to form anoptical print head having 7,680 light-emitting parts, it is possible toincrease the printing speed 40/16=2.5 times as compared with the casewhere the number (m) of time divisions is 40 described above withreference to FIG. 3.

Another known way to increase the printing speed is to increase thecurrent that is passed through the individual light-emitting parts sothat they produce higher light output. However, in cases where thecurrent cannot be increased, for example when the current before beingincreased is already close to the maximum current permitted by thelight-emitting parts, or when the current is intentionally kept low toextend the working life of the light-emitting parts, it is preferable toincrease the printing speed by reducing the effective number of timedivisions as described above.

In this way, while using the same driving IC, it is possible to adapt toa change in the printing speed required in a print head by changing theeffective number of time divisions, and thereby adapt to a change in thefunctions of the print head.

Second Embodiment

Next, a second embodiment of the invention will be described. FIG. 8 isa plan view showing a principal portion of the optical print head ofthis embodiment. FIG. 9 is a plan view showing a principal portion ofthe light-emitting device of this embodiment. In this embodiment, thedriving IC is configured in the same manner as in the first embodiment,and thus as shown in FIGS. 1 and 2, and operates in the same manner asin the first embodiment, and thus as shown in the timing chart of FIG.3. In FIGS. 8 and 9, such elements as are found also in FIGS. 5 and 6are identified with the same reference numerals, and their explanationswill not be repeated.

With respect to the conductors that connect the driving IC 1 and thelight-emitting devices 22 together, in the first embodiment, as shown inFIG. 5, the first conductors 23-1 are arranged below the light-emittingdevices 22, the second conductors 23-2 are arranged above the lightemitting devices 22, and these conductors are connected to thelight-emitting devices 22 on both sides thereof by wire-bonded leads. Bycontrast, in this embodiment, as shown in FIG. 8, the second conductors23-2, which are connected to the output terminals CD1 to CD40 for groupselection of the driving IC 1, are arranged below the light-emittingdevices 22, the first conductors 23-1, which are connected to the outputterminals DO1 to DO48 of the driving IC 1, are arranged further belowthe second conductors 23-2, and these conductors are connected to thelight-emitting devices 22 on one side thereof by wire-bonded leads. Thatis, the portions of the conductor patterns of the first and secondconductors 23-1 and 23-2 which have substantially the same length as thetotal length along which the light-emitting devices 22 are arranged arearranged on only one side of the row of the light-emitting devices 22.

As in the first embodiment, the light-emitting devices 22 that areelectrically connected to the driving IC 1 by the first and secondconductors 23-1 and 23-2 in this way each have a plurality of (p×n=384)light-emitting parts 26 arranged on the top surface thereof, along thelonger sides thereof and at a density of about 1,200 DPI. Theselight-emitting parts 26 are formed independently of each other so thatthey can be driven on a time-division basis. Specifically, thelight-emitting parts 26 are divided into a plurality of (p) groups sothat they can be driven in groups of n. As in the first embodiment, inthis embodiment is dealt with an example in which the light-emittingparts 26 are divided into 8 groups on the basis of the remainder thatremains when the number representing the order of arrangement of eachlight-emitting part 26 is divided by a division number p (8).

As shown in FIG. 9, on the light-emitting device 22 are laid eightcommon electrodes 27, consisting of a common electrode 27-1 that isconnected to the light-emitting parts 26 belonging to the first group ona common basis, a common electrode 27-2 that is connected to thelight-emitting parts 26 belonging to the second group on a common basis,. . . , and a common electrode 27-8. Also laid are n (48) individualelectrodes 28 of which each is connected to eight consecutivelight-emitting parts 26. Whereas, in the first embodiment, the commonelectrodes 27 and the individual electrodes 28 are arranged on bothsides of the light-emitting parts 26 and along the longer sides of thelight-emitting device 22 as shown in FIG. 6, in this embodiment, theyare arranged on one side of the light-emitting parts 26 and along thelonger sides of the light-emitting device 22.

Thus, in this embodiment, the configuration and operation of the opticalprint head are the same as in the first embodiment except for theconfiguration of the light-emitting device 22 and its relationship withthe first and second conductors 23-1 and 23-2. Therefore, no furtherexplanations of this embodiment will be given, and instead reference isto be made to the description of the first embodiment.

Third Embodiment

FIG. 10 is a circuit block diagram showing the basic configuration ofthe driving IC of a third embodiment of the invention. FIG. 11 is acircuit block diagram of a principal portion of the circuit blockdiagram of FIG. 10, specifically the portion associated with one DO1among a plurality of output terminals DO1 to DO96. First, descriptionswill be given with reference mainly to these figures.

The driving IC 1 shown in FIG. 10 differs from the driving IC 1 shown inFIG. 1 in that the data signal storage circuit 54 has a multiple-inputshift register 58 of an n×m bit type that takes in data signals seriallyfed in via data input terminals SI1 to SI4 in synchronism with the clocksignal CLKI and that outputs the data signals serially via data outputterminals SO1 to SO4. Therefore, such elements as are found also in FIG.1 are identified with the same reference numerals, and theirexplanations will not be repeated. The individual terminal section DOconsists of a plurality of (n) output terminals DO1 to DO96 for drivinglight-emitting devices, and the common terminal section CD consists of aplurality of (m) output terminals CD1 to CD4 for selecting groups.

The following descriptions deal with a case where n=96 and m=4 as shownin the figures. However, it is to be understood that the presentinvention may be implemented in any other manner than specificallydescribed below. When n=96 and m=4, the shift register 58 is of a 384bit type, and accordingly the latch circuit 9 also is of a 384 bit typebecause, on the basis of the load signal LOAD1, it needs to take in, ingroups of 384 bits, the data signals taken in by the shift register 58.

In the drive circuit 5, the selecting circuit 11A sequentially selectsand outputs, in groups of n, the m×n (384) data signals output from thelatch circuit 9, and the first drive circuit 12A, which outputs apredetermined current via the output terminals DO1 to DO96 on the basisof the output of the first selecting circuit 11A, is of an n (96) bittype. Moreover, the correction data storage circuit 10 stores n×m (384)correction data signals for output correction, and the second selectingcircuit 11B sequentially selects, in groups of n, the n×m (384)correction data signals output from the correction data storage circuit10. Furthermore, the second drive circuit 12B, for correction, is of ann (96) bit type because it outputs, as driving signals via the outputterminals DO1 to DO96, current outputs of which the current is adjustedon the basis of the output from the second selecting circuit 11B forcorrection data.

As in the first embodiment, the storage circuit 10 is configured as, forexample, a latch circuit of an S×n×m bit type so that it can store n×m(384) correction data signals each consisting of S bits (for example, 3bits). The writing of correction data signals to the correction datastorage circuit 10 is achieved on the basis of the signals fed parallel,in groups of n×m, from the shift register 58.

The division timing signal generator circuit 14 here, as opposed to thatof the first embodiment, produces division timing signals (DIV1 to DIV4)on the basis of two signals DIVSEL1 and DIVSEL2 that are supplied fromoutside to determine the timing of time division, as shown in the truthtable in Table 1.

TABLE 1 DIVSEL1 DIVSEL2 Selected H H DIV4 H L DIV3 L H DIV2 L L DIV1

Next, with reference to FIG. 11, the flow of data will be described withrespect mainly to one output terminal DO1. As the division timingsignals DIV1 to DIV4 are turned to H level one by one, four AND gatecircuits provided in the first selecting circuit 11A and connected tothose division timing signals DIV1 to DIV4 and to the latch circuit 9are opened one by one. Thus, the data signals corresponding to the wholeIC that are stored in the latch circuit 9 (384 pieces of on/off data)are selectively output through the AND gate circuit that is open at eachmoment. In the example shown in FIG. 11, the first to fourth datasignals within one IC are sequentially used to drive the drive circuit12. Similarly, as the division timing signals DIV1 to DIV4 are turned toH level one by one, AND gates circuit provided in sets of three in thesecond selecting circuit 11B are opened one set after another. Thus, thethree-bit correction data signals stored in the correction data storagecircuit 10 are selectively output through the set of AND gate circuitsthat is open at each moment. The output of the correction data storagecircuit 10 is fed to the drive circuit 12 so as to selectively operate,together with the data signals fed from the latch circuit 9 through thefirst selecting circuit 11A, the three current amplifiers 12 b to 12 d.

Next, the second drive section 3 will be described. The second drivesection 3 is a circuit for selectively switching one of the outputterminals CD1 to CD4 to the ground potential VSS, and performs theswitching in synchronism with the division timing signals DIV1 to DIV4.The switching may be achieved by the use of other signals that aresynchronous with the division timing signals DIV1 to DIV4.

FIG. 14 is a plan view showing a principal portion of an example of anoptical print head 20, which employs, as the driving ICs 1, the drivingIC described in the third and fourth embodiments of the invention. Thisoptical print head 20 has a plurality, for example 20, of light-emittingdevices 22 arranged in a row on an insulating substrate 21, and hasdriving ICs 1 arranged in a row on one side of and adjacent to thelight-emitting devices 22 in such a way that the driving ICs 1correspond one to one to the light-emitting devices 22. In this example,the driving ICs 1 are arranged on one side of the light-emitting devices22. In a case where the driving ICs 1 are arranged on both sides of thelight-emitting devices 22, they are arranged in such a way that one ofthe light emitting devices 22 corresponds to two of the driving ICs 1.Between the light-emitting devices 22 and the driving ICs 1 are laidconductors 23 for connecting them together. The conductors 23 may berealized by direct connection using wire-bonded leads of gold or thelike, or indirect connection using wire-bonded leads in combination withan interposed relay pattern, or with high-density flexible wiresconnected by the use of anisotropic conductive adhesive.

On the substrate 21, a plurality of conductor patterns 24 for signaltransmission and power supply are laid so as to extend in the directionof arrangement of the light-emitting devices 22. Between the driving ICs1 and the conductor patterns 24 are laid conductors 25 similar to theconductors 23.

Each light-emitting device 22 has a plurality of (m×n=384)light-emitting parts 26 arranged on the top surface thereof, along thelonger sides thereof. These light-emitting parts 26 are formedindependently of each other so that they can be driven on atime-division basis. Specifically, the light-emitting parts 26 aredivided into a plurality m of groups so that they can be driven group bygroup on a time-division basis. In this example, the light-emittingparts 26 are divided into 4 groups on the basis of the remainder thatremains when the number representing the order of arrangement of eachlight-emitting part 26 is divided by 4. Specifically, here, of all thelight-emitting parts 26, the first, fifth, ninth, . . . belong to afirst group, the second, sixth, tenth, . . . belong to a second group,the third, seventh, eleventh, . . . belong to a third group, and thefourth, eighth, twelfth, . . . belong to a fourth group.

Moreover, on the light-emitting device 22 are laid four commonelectrodes 27, consisting of a common electrode 27-1 that is connectedto the light-emitting parts 26 belonging to the first group on a commonbasis, a common electrode 27-2 that is connected to the light-emittingparts 26 belonging to the second group on a common basis, a commonelectrode 27-3, and a common electrode 27-4. Also laid are n (96)individual electrodes 28 of which each is connected to four consecutivelight-emitting parts 26. The individual electrodes 28 are connectedindividually to the output terminals DO1 to DO96 of the correspondingdriving IC 1, and the common electrodes 27 are connected to the outputterminals CD1, CD2, CD3, and CD4 of the same driving IC 1. By selectingone among the common electrodes 27 and energizing appropriate ones ofthe individual electrodes DO, it is possible to light the light-emittingparts 26 on a time-division basis, one-fourth of them at a time.

In this example, there are provided L (20) light-emitting devices 22.Thus, in the entire head 20 are provided L×m×n=20×4×96=7,680light-emitting parts 26 in total.

FIG. 15 is a circuit block diagram of the optical print head 20. Theoptical print head 20 has 20 light-emitting devices 22 arranged in arow. The numbers starting with a # represent the serial numbers of thelight-emitting parts 26 throughout the optical print head 20. Theindividual electrodes 28 are each connected to one of the light-emittingparts 26 (to the anode thereof) of each of the four groups on a commonbasis, and the cathodes of the light-emitting parts 26 belonging to eachof the four groups are connected to the common electrodes 27-1, 27-2,27-3, and 27-4 respectively. The individual electrodes 28 are connectedto the individual terminals DO1 to DO96 of the corresponding driving IC1. The common electrodes 27-1, 27-2, 27-3, and 27-4 are connected to theoutput terminals CD1, CD2, CD3, and CD4 respectively. The data inputterminals SI1 to SI4 of the first driving IC 1 are connected to the dataoutput terminals SO1 to SO4 of the second driving IC 1. Likewise, thedata input terminals SI1 to SI4 of the second to nineteenth driving ICs1 are connected to the data output terminals SO1 to SO4 of the drivingICs 1 that are assigned numbers greater by one than those. Data signalsfed in from outside are fed to the data input terminals SI1 to SI4 ofthe twentieth driving IC 1. The driving ICs 1 each receive a supplyvoltage VDD1, external signals DIVSEL1 and DIVSEL2, a load signal LOAD1,and other signals. It is to be noted that, in FIG. 15, SI represents SI1to SI4 and SO represents SO1 to SO4.

Next, the operation of the optical print head 20 described above,including the operation of the driving IC 1 of the third embodiment,will be described with reference to, in addition to FIGS. 10 and 11, anexample of the circuit configuration of the optical print head shown inFIG. 15 and the timing chart shown in FIG. 13. Here, it is assumed thatthe correction data to be stored in the storage circuit 10 has alreadybeen stored therein.

First, the set signal SET is turned from L level to H level. As aresult, the storage circuit 10 is brought into a write disable state.

Data signals (7,680 signals) are fed sequentially, in groups of r, tothe data input terminals SI1 to SI4 of the twentieth driving IC 1, andare taken in sequentially by the multiple-input shift registers 58 ofthe individual driving ICs 1 in synchronism with the clock signal CLK1.Here, the data signals that are fed to the input terminals SI1 to SI4are fed in in a form divided in advance so as to correspond to the fourgroups of light-emitting parts; specifically, the first, fifth, ninth, .. . data signals are fed to the input terminals SI1, the second, sixth,tenth, . . . data signals are fed to the input terminals SI2, and soforth. When the input of data signals to the shift register 58 of onedriving IC 1 is complete, the data signals are fed, via the outputterminals SO1 to SO4 thereof, to the shift register 58 of the adjacentdriving IC 1. Inputting the data signals via multiple paths in this wayhelps greatly reduce the time required to input the data signals ascompared with a case where they are input via a single path.

When the input of data signals corresponding to one line is complete,the load signal LOAD 1 is held at H level for a predetermined period sothat the n×m data signals held in the shift registers 8 of theindividual driving ICs 1 are input. Here, the latch circuit 9 selects(latches) data signals on a trailing edge of the load signal LOAD 1, andtherefore the n×m data signals taken in by the shift register 8 areinput to the latch circuit 9 and are stored therein.

Immediately after the load signal LOAD 1 is turned from H level to Llevel, the external signals DIVSEL1 and DIVSEL2 indicating the timing oflight emission are both held at L level, and simultaneously, of thedivision timing signals output from the division timing signal generatorcircuit 14, only DIV1 is turned from L level to H level. Immediatelythereafter, the external strobe signal (inverted STB) indicating thetiming of emission is turned from H level to L level and is then held atL level for a predetermined period, during which the light-emittingdevices are lit selectively.

Immediately after the load signal LOAD 1 is turned from H level to Llevel, the external signals DIVSEL1 and DIVSEL2 indicating the timing oflight emission are both held at L level, and simultaneously, of thedivision timing signals output from the division timing signal generatorcircuit 14, only DIV1 is turned form L level to H level. Immediatelythereafter, the external strobe signal (inverted STB) indicating thetiming of the light emission is turned from H level to L level and isthen held at L level for a predetermined period, during which thelight-emitting devices are lit selectively.

Then, by changing the combination of the external signals DIVSEL1 andDIVSEL2, only DIV2 among the division timing signal is turned to Hlevel. Then, in similar manners, only DIV3, and then only DIV4, isturned to H level.

As the division timing signals DIV1 to DIV4 are switched in this way,the selecting circuit 11 selects and outputs, from one position afteranother, the data signals stored in the latch circuit 9 or thecorrections data storage circuit 10. For example, the division timingsignal DIV1 selects the first, fifth, . . . , and 7,677th data signals,and the division timing signal DIV2 selects the second, sixth, . . . ,and 7,678th data signals.

These data signals (with 3-bit correction data signals added thereto asrequired) are fed to the drive circuit 12. On the basis of the datasignals and the correction data signals added thereto, the drive circuit12 selectively operates the four current amplifiers 12 a to 12 d so thattheir output currents are fed via the output terminals DO to theindividual electrodes 28 of the light-emitting devices 22.

In this state, the individual electrodes 28 of all the light-emittingdevices 22 are ready to receive currents corresponding to the datasignals of correction data signals. However, here, only one-fourth ofthe light-emitting parts 26 are grounded through the common electrodes27. Thus, in this example, only every forth light-emitting part 26 isselectively lit while the strobe signal (inverted STB) is held at Llevel.

By driving the light-emitting parts on a time-division basis, ie.one-fourth of them at a time, to achieve light emission for one line asdescribed above, and then repeating this sequentially, it is possible toachieve the exposure of a whole screen.

As described above, despite time-division driving, data signalscorresponding to one line can be input in a single sequence ofprocessing. Thus, there is no need to input data signals sequentially ata number of different times equal to the number of divisions as requiredin conventional configurations. In particular, the number (m) of groupsis set equal to the number (r) of data input terminals. This makes itpossible to input data signals in a form divided in advance so as tocorrespond to the group, and thus makes the input of data signalseasier.

The driving IC 1 of this embodiment can easily be adapted for thedriving of light-emitting devise having a resolution other than 1,200DPI. Now, examples of such adaptation will be described with referenceto FIG. 16 to 21, which schematically show various configurations, andFIG. 22 to 25, which show timing charts. FIG. 16 schematically shows theconfiguration corresponding to the optical print head configured asdescribed above.

FIG. 17 shows the configuration of an optical print head that employs alight-emitting device having two common electrodes (M=2), 96 individualelectrodes (N=96), and a resolution of 600 DPI. That is, this opticalprint head employs, as the light-emitting device 22, a light-emittingdevice of a two division type that has an external shape similar to thatof the light-emitting device 22 shown in FIG. 14 and described earlierbut that has light-emitting parts 26 arranged at half the densitythereof and divide into two groups(M=2), i.e. odd-numbered numbered andeven-numberedgroups. The driving IC 1, by using two inputs SI1 and AI2,performs the input of data signals corresponding to one line with 1,920clock pulses and, by using the other two inputs SI3 and SI4,simultaneously performs the input of data signals corresponding to thenext line. To cope with these changes, data signals need to be input inan accordingly altered manner. Except for these changes, this opticalprint head has the same configuration as the optical print head 20 (FIG.16) described earlier. Thus, as shown in a timing chart in FIG. 22,after data signals corresponding to two lines have been taken in in asingle data input sequence, the first group (the odd-numbered datasignals) of the first line is selected by the division timing signalDIV1, then the second group (the even-numbered data signals) of thefirst line is selected by the division timing signal DIV2, then thefirst group (the odd-numbered data signal) of the second line isselected by the division timing signal DIV3, and then the second group(the even-numbered data signal) of the second line is selected by thedivision timing signal DIV4.

Here, by leaving the other two inputs SI3 and SI4 unused as shown inFIG. 18, the optical print head is so configured as to deal with onlydata signals corresponding to one line This makes it possible to use thedriving IC 1 designed for 1,200 DPI to drive a 600 DPI light-emittingdevice 22.

FIG. 19 shows the configuration of an optical print head that employs a300 DRI light-emitting device. That is, this optical print head employsas the light-emitting device 22 a light-emitting device of anon-division type that has an external shape similar to that of thelight-emitting device 22 shown in FIG. 14 and described earlier but thathas light-emitting portions 26 arranged at one-fourth of the densitythereof and grouped into a single group (M=1). As shown in a timingchart in FIG. 23, the input of data signals to the driving IC 1 isperformed by using four inputs SI1 to SI4 so that data signalscorresponding to four lines are input with 1,920 clock pulses. To copewith these changes, data signals need to be input in an accordinglyaltered manner. Except for these changes, this optical print head hasthe same configuration as the optical print head 20 (FIG. 16) describedearlier. This makes it possible to use the driving IC 1 designed for1,200 DPI to drive a 300 DPI light-emitting device 22. Moreover, it ispossible to input data signals corresponding to four lines in a singledata input sequence. This helps enhance the data processing performanceperformance and increase the printing speed.

FIG. 20 shows the configuration of an optical print head that employs600 DPI light-emitting devices. That is, this optical print head employsas the light-emitting device 22 two light-emitting devices of a twodivision type that each have the same length as the light-emittingdevice 22 shown in FIG. 14 and describing earlier but that havelight-emitting parts 26 arranged at half the density thereof, i.e. 600DPI, and divided into two groups (M=2). These light-emitting devices arearranged along the longer sides of themselves and are connecting to thedriving IC by multiplex conductors. As shown in a timing chart in FIG.24, the driving IC 1 performs the input of odd-numbered data signals ofone light-emitting device by using one input SI1 thereto, performs theinput o even-numbered data signals of that light-emitting device byusing the next input SI2, performs the input o odd-numbered data signalsof the light-emitting devices by using the next unput SI3, and performsthe input of even-numbered data signals of that light-emitting device byusing the next input SI4 so that data signals corresponding to one lineare input with 960 clock pulses. To cope with these changes, datasignals need to be input in an accordingly altered manner. Except forthese changes, this optical print head has the same configuration as theoptical print head 20 (FIG. 16) described earlier. This makes itpossible to use the driving IC1 designed for 1,200 DPI to drive 600 DPIlight-emitting devices 22. Moreover, it is possible to form a unit(block) consisting of one driving IC and two light-emitting devices andarrange a plurality of such units along the longer sides of thesubstrate 21. This helps reduce the number of diving ICs.

FIG. 21 shows the configuration of an optical print head that employs300 DPI light-emitting devices. That is, this optical print head employsas the light-emitting device 22 four light-emitting devices of anon-division type that each have the same length as the light-emittingdevice 22 shown in FIG. 14 and described earlier but that havelight-emitting parts 26 arranged at one-fourth of the density thereof,i.e. 300 DPI, and grouped into a single group (M==1). Theselight-emitting devices are arranged along the longer sides of themselvesand are connected to the driving IC by multiplex conductors. As shown ina timing chart in FIG. 25, the driving IC 1 performs the input of datasignals of the first light-emitting device by using one input SI1thereto, performs the input of data signals of the second light-emittingdevice by using the next input SI2, performs the input of data signalsof the third light-emitting device by using the next input SI3 andperforms the input of data signals of the fourth light-emitting deviceby using the next input SI4 so that data signals corresponding to oneline are input with 480 clocks. To cope with these changes, data signalsneeds to be input in an accordingly altered manner. Except for thesechanges, this optical print head has the same configuration as theoptical print head 20 (FIG. 16) described earlier. This makes itpossible to. use the driving IC 1 designed for 1,200 DPI to drive 300DPI light-emitting devices 22. it is possible to form a unit (block)consisting of one driving IC and four light-emitting devices and arrangea plurality of such units along the longer sides of the substrate 21.helps reduce the number of driving ICs.

Fourth Embodiment

Next, a fourth embodiment of the invention will be described. FIG. 26 isa circuit block diagram of a principal portion of the driving IC 1 ofthe fourth embodiment, specifically the portion associated with one DO1among a plurality of output terminals DO1 to DO96. In this embodiment, alatch circuit 11C is used that stores a smaller number of data signalsthan the data signals stored in the shift register 58. Now, thisembodiment will be described with reference to FIGS. 26 and 27.

This embodiment differs greatly from the third embodiment in that theselecting circuit that supplies, in groups of n, the plurality of (m×n)data signals stored in the shift register to the driving circuit 12 isrealized with a latch circuit 11C that stores the same number of datasignals as the output terminals DO1 to DO96 (n=96) and a selectingcircuit 11A that selectively feeds data signals to the latch circuit11C.

As shown in FIG. 26, the plurality of (m×n=384) data signals stored inthe shift register 58 are fed through the selecting circuit 11A composedof logic gate circuits to the latch circuit 11C. The latch circuit 11Cis configured as a latch of an n (96) bit type that stores the samenumber of data signals as the output terminals DO1 to DO96, and takes indata signals in groups of n on the basis of the signal LOAD 1. On thebasis of the division timing signals DIV1 to DIV4 output from thedivision timing signal generator circuit 14, the selecting circuit 11Aselects n data signals among the plurality of (m×n=384) data signalsoutput from the shift register 58, and feeds them to the latch circuit11C. The data signals stored in the shift register 58 are sequentiallyfed to the latch circuit 11C as a result of such selecting operationrepeated m times. The n data signals output from the latch circuit 11Care fed to the driving circuit 12 while the strobe signal (inverted STB)is held at L level.

The division timing signal generator circuit 14 may be configured asshown in FIG. 12. Here, however, the division timing signal generatorcircuit 14 is configured, as shown in FIG. 28, so as to count pulses ofone external timing signal DIVSEL and output the count. That is, forexample as shown in FIG. 28, the division timing signal generatorcircuit 14 is configured as a counter composed of two flip-flops FF1 andFF2 and a plurality of (for example, four) logic gate circuits G1 to G4.

Specifically, the JK flip-flop FF1 receives a supply voltage VDD1, whichis at H level, at its input terminals J and K, receives the externalsignal DIVSEL at its clock input terminal CL, and receives the resetsignal RESET at its reset input terminal R. The flip-flop FF1 outputs asignal QA at the output terminal Q thereof, and outputs a signal{overscore (QA)} at the output terminal {overscore (Q)}. The JKflip-flop FF2 receives the signal QA at its input terminals J and K,receives the external signal DIVSEL at its clock input terminal CL, andreceives the reset signal RESET at its reset input terminal R. Theflip-flop FF2 outputs a signal QB at its output terminal Q, and outputsa signal {overscore (QB)} at its output terminal {overscore (Q)}. Thelogic gate circuit G1 performs AND operation on the external signalDIVSEL, the signal QA, and the signal {overscore (QB)}, and outputs thedivision timing signal DIV1. The logic gate circuit G2 performs ANDoperation on the external signal DIVSEL, the signal {overscore (QA)},and the signal QB, and outputs the division timing signal DIV2. Thelogic gate circuit G3 performs AND operation on the external signalDIVSEL, the signal QA, and the signal QB, and outputs the divisiontiming signal DIV3. The logic gate circuit G4 performs AND operation onthe external signal DIVSEL, the signal {overscore (QA)}, and the signal{overscore (QB)}, and outputs the division timing signal DIV4.

The operation of this embodiment is shown in a timing chart in FIG. 27.As shown in this figure, after data signals corresponding to one linehave been taken in through the four inputs SI1 to SI4 with 1,920 clockpulses, it is not possible to take in data signals corresponding to thenext line until the driving based on the data signals of the first lineis complete. This reduces the processing speed, but instead helps reducethe number of circuit elements provided in the driving IC and therebymake the IC compact and inexpensive. Thus, this embodiment is suitablefor optical print heads in which priority is given to miniaturizationand cost reduction rather than the processing speed.

In any of the embodiments described above, it is possible to use, aslight-emitting devices, not only light-emitting diodes having a PNjunction but also light-emitting devices having light-emitting partswith any other structure arranged thereon, such as light-emitting diodeshaving a PNPN junction (light-emitting thyristors). Moreover, it ispossible to use not only light-emitting devices having light-emittingparts arranged in a row but also those having light-emitting partsarranged in a zigzag or in two or more rows.

In the third and fourth embodiments, instead of arranging the drivingICs on one side of the light-emitting devices, it is also possible, asin the first embodiment, to arrange the driving ICs on both sides of thelight-emitting devices. In such cases, it is preferable to uselight-emitting devices having a resolution twice as high, for examplelight-emitting devices having a resolution of 2,400 DPI. Moreover, byleaving either the individual terminal section or common terminalsection of the driving IC open, or by any other method, it is possibleto selectively use its first drive section 2 or second drive section 3alone.

In the first and second embodiments, it is possible to use, as in thethird and fourth embodiments, a multiple-input shift register to whichdata signals are fed parallel via a plurality of input terminals.

INDUSTRIAL APPLICABILITY

As described above, according to the present invention, it is possibleto perform time-division driving while processing data signals in quitethe same manner as in conventional static driving. This helps maintaincompatibility with static driving. Moreover, by making time-divisiondriving possible, it is possible to reduce the number of driver ICs andthe number and density of wire-bonded leads. Moreover, it is possible toconnect driving ICs and light-emitting devices together in variouscombinations. Moreover, it is easy to change the printing speed bymodifying input data signals so as to change the effective number oftime divisions. Moreover, it is possible to realize a high-resolutionoptical print head even in a case where the density (resolution) ofconductor patterns laid on a substrate is low.

Moreover, it is possible to realize a driver IC that can cope with aplurality of types of light-emitting device with different resolutions.Moreover, it is possible to realize a driver IC and an optical printhead that permit high-speed input of data signals. Furthermore, it ispossible to reduce the size, reduce the cost, and increase the printingspeed of an optical print head.

1. A driving IC device for supplying a driving current to alight-emitting device having a plurality of light-emitting partsarranged in a row, the driving IC device comprising n first outputterminals each connected to one terminal of m light-emitting parts and afirst drive section connected to the first output terminals, wherein thefirst drive section comprises: a data signal storage circuit for storingat least n×m data signals fed in a sequential order via r inputterminals; a data selecting circuit for selecting and extracting, ingroups of n, the data signals stored in the data signal storage circuitwithout changing the sequential order; and a drive circuit foroutputting drive signals individually to the first output terminals on abasis of the data signals selected by the data selecting circuit.
 2. Adriving IC device as claimed in claim 1, further comprising m secondoutput terminals each connected to another terminal of n light-emittingparts and a second drive section for selectively connecting one of thesecond output terminals to a predetermined potential.
 3. A driving ICdevice as claimed in claim 1, wherein the data signal storage circuit iscomposed of a shift register that stores n×m data signals when r datasignals are fed in and a latch circuit that stores n×m data signals, andthe data selecting circuit selects and extracts, in groups of n, thedata signals stored in the latch circuit.
 4. A driving IC device asclaimed in claim 3, further comprising m second output terminals eachconnected to another terminal of n light-emitting parts and a seconddrive section for selectively connecting one of the second outputterminals to a predetermined potential.
 5. A driving IC device asclaimed in claim 1, wherein the data signal storage circuit is composedof a shift register that stores n×m data signals when r data signals arefed in, and the data selecting circuit is composed of a latch circuitthat selects and extracts, in groups of n, the data signals stored inthe shift register and that stores the n data signals thus extracted. 6.A driving IC device as claimed in claim 5, further comprising m secondoutput terminals each connected to another terminal of n light-emittingparts and a second drive section for selectively connecting one of thesecond output terminals to a predetermined potential.
 7. A driving ICdevice as claimed in claim 1, wherein the first drive section furthercomprises a correction data storage circuit for storing n×m correctiondata signals with which to correct the n×m data signals.
 8. A driving ICdevice as claimed in claim 1, wherein the driving IC device is fordriving a light-emitting device having m or less groups of nlight-emitting parts group by group on a time-division basis.
 9. Adriving IC device as claimed in claim 1, further comprising: k×m (wherek is an integer equal to or greater than 2) second output terminals eachconnected to another terminal of n of the light-emitting parts; and asecond drive section for selectively connecting the second outputterminals to a predetermined potential, wherein, in the data signalstorage circuit, n×m data signals are stored for each of k lines.
 10. Adriving IC device as claimed in claim 9, wherein the number r of inputterminals is set to be equal to the number k×m of second outputterminals.
 11. A driving IC device as claimed in claim 1, furthercomprising: m second output terminals each connected to another terminalof n of the light-emitting parts; and a second drive section forselectively connecting the second output terminals to a predeterminedpotential, wherein, when the driving IC device is connected to k of thelight-emitting device each having n×(m/k) (where k is a divisor of m) ofthe light-emitting parts, the driving IC device drives thelight-emitting devices in groups of (m/k) on the time-division basis.12. A driving IC device as claimed in claim 11, wherein the number r ofinput terminals is set to be equal to the number m of second outputterminals.
 13. A driving IC device for supplying a driving current to alight-emitting device having a plurality of light-emitting partsarranged in a row, the driving IC device comprising n first outputterminals each connected to one terminal of m light-emitting parts, msecond output terminals each connected to another terminal of nlight-emitting parts, a first drive section connected to the firstoutput terminals, a second drive section connected to the second outputterminals, and a timing control circuit, wherein the first drive sectioncomprises: a data signal storage circuit for storing at least n×m datasignals fed in a sequential order via r input terminals; a divisiontiming generating circuit for generating m division timing signals froma signal fed from the timing control circuit; a data selecting circuitfor selecting and extracting, in groups of n, the data signals stored inthe data signal storage circuit on a basis of the m division timingsignals fed from the division timing generating circuit without changingthe sequential order; and a drive circuit for outputting drive signalsindividually to the first output terminals on a basis of the datasignals selected by the data selecting circuit, and the second drivesection switches sequentially among the m second output terminals on abasis of the m division timing signals.
 14. A driving IC device asclaimed in claim 13, wherein the number r of input terminals is equal tothe number m of second output terminals.
 15. A driving IC device asclaimed in claim 13, wherein the first drive section further comprises acorrection data storage circuit for storing n×m correction data signalswith which to correct the n×m data signals.
 16. A driving IC device asclaimed in claim 13, wherein the driving IC device is for driving alight-emitting device having m or less groups of n light-emitting partsgroup by group on a time-division basis.
 17. An optical print headcomprising a light-emitting device having a plurality of light-emittingparts and a driving IC device for supplying a driving current to thelight-emitting parts of the light-emitting device, wherein thelight-emitting device comprises n first electrodes each connected to oneterminal of a plurality of light-emitting parts, the driving IC devicecomprises n first output terminals connected individually to the firstelectrodes of the light-emitting device and a first drive section foroutputting the driving current via the first output terminals, and thefirst drive section comprises a data signal storage circuit for storingat least n×m data signals fed in sequential order via r input terminals,a data selecting circuit for selecting and extracting, in groups of n,the data signals stored in the data signal storage circuit withoutchanging the sequential order, and a drive circuit for outputting drivesignals individually to the first output terminals on a basis of thedata signals selected by the data selecting circuit.
 18. An opticalprint head as claimed in claim 17, wherein the driving IC device furthercomprises m second output terminals each connected to another terminalof n light-emitting parts and a second drive section for selectivelyconnecting one of the second output terminals to a predeterminedpotential.
 19. An optical print head as claimed in claim 17, wherein thedata signal storage circuit is composed of a shift register that storesn×m data signals when r data signals are fed in and a latch circuit thatstores n×m data signals, and the data selecting circuit selects andextracts, in groups of n, the data signals stored in the latch circuit.20. An optical print head as claimed in claim 19, further comprising msecond output terminals each connected to another terminal of nlight-emitting parts and a second drive section for selectivelyconnecting one of the second output terminals to a predeterminedpotential.
 21. An optical print head as claimed in claim. 17, whereinthe data signal storage circuit is composed of a shift register thatstores n×m data signals when r data signals are fed in, and the dataselecting circuit is composed of a latch circuit that selects andextracts, in groups of n, the data signals stored in the shift registerand that stores the n data signals thus extracted.
 22. An optical printhead as claimed in claim 21, further comprising m second outputterminals each connected to another terminal of n light-emitting partsand a second drive section for selectively connecting one of the secondoutput terminals to a predetermined potential.
 23. An optical print headas claimed in claim 17, wherein the first drive section furthercomprises a correction data storage circuit for storing n×m correctiondata signals with which to correct the n×m data signals.
 24. An opticalprint head as claimed in claim 17, wherein the driving IC device is fordriving the light-emitting device having m or less groups of nlight-emitting parts group by group on a time-division basis.
 25. Anoptical print head as claimed in claim 17, wherein the driving IC devicefurther comprises: k×m (where k is an integer equal to or greater than2) second output terminals each connected to another terminal of n ofthe light-emitting parts; and a second drive section for selectivelyconnecting the second output terminals to a predetermined potential, andwherein, in the data signal storage circuit, n×m data signals are storedfor each of k lines.
 26. An optical print head as claimed in claim 25,wherein the number r of input terminals is set to be equal to the numberk×m of second output terminals.
 27. An optical print head as claimed inclaim 17, wherein there are provided k of the light-emitting device eachhaving n×(m/k) (where k is a divisor of m) of the light-emitting parts,wherein the drive IC device further comprises: m second output terminalseach connected to another terminal of n of the light-emitting parts; anda second drive section for selectively connecting the second outputterminals to a predetermined potential, and wherein the light-emittingdevices are driven in groups of (m/k) on a time-division basis.
 28. Anoptical print head as claimed in claim 27, wherein the number r of inputterminals is set to be equal to the number m of second output terminals.29. An optical print head comprising a light-emitting device having aplurality of light-emitting parts and a driving IC device for supplyinga driving current to the light-emitting parts of the light-emittingdevice, wherein the light-emitting device comprises n first electrodeseach connected to one terminal of m light-emitting parts and m secondelectrodes each connected to another terminal of n light-emitting parts,the driving IC device comprises n first output terminals connectedindividually to the first electrodes of the light-emitting device, afirst drive section for outputting the driving current via the firstoutput terminals, m second output terminals connected individually tothe second electrodes of the light-emitting device, a second drivesection for keeping one of the second output terminals at apredetermined potential so as to make the light-emitting part connectedthereto active, and a timing control circuit for outputting m divisiontiming signals, the first drive section comprises a data signal storagecircuit for storing at least n×m data signals fed in sequentially via rinput terminals, a data selecting circuit for selecting and extracting,in groups of n, the data signals stored in the data signal storagecircuit on a basis of the m division timing signals fed from the timingcontrol circuit, and a drive circuit for outputting drive signalsindividually to the first output terminals on a basis of the datasignals selected by the data selecting circuit, and the second drivesection switches sequentially among the m second output terminals on abasis of the m division timing signals.
 30. An optical print head asclaimed in claim 29, wherein the number r of input terminals is equal tothe number m of second output terminals.
 31. An optical print head asclaimed in claim 29, wherein the first drive section further comprises acorrection data storage circuit for storing n×m correction data signalswith which to correct the n×m data signals.
 32. An optical print head asclaimed in claim 29, wherein the driving IC device is for driving thelight-emitting device having m or less groups of n light-emitting partsgroup by group on a time-division basis.